Details of Nehalem

After the gossip concerning Intel codename Nehalm last article, Intel had finally given the explanation about Nehalem. Intel revealed details about Nehalem.

Nehalem will be a scalable architecture with some products with having onboard memory controller onpackage GPU, and up to 16 threads per chip. Nehalem architected on 45nm Nehalem is a new design, having its roots in the four issue Core 2 Duo architecture. Nehalem to be the first true dynamically scalable microarchitecture. This means Nehalem is only designed to be mixed with varied amounts of cache and different features in order to produce processors, not to take up to eight cores on a single die.
Intel wants to increase the performance per clock as well as the frequencies that the CPUs are able to run at within a similar power envelope.
In Q1 2008, Intel revealed information on introducing into the 45nm technology. The 45nm technology have an ability to add 2x more transistors to a chip maintaining a static die size and thermal envelope allow Intel to add features that can greatly increase overall performance. The result is increased performance and increased energy efficiency. Intel also will reveal the inclusion of SSE4 into the instruction on the processors and will have larger caches. Intel told 8MB L2 caches are expected to become the standard on desktop models, raising the transistor count to about 410M transistors for dual core CPU and 820M transistors for quad core and will using 1333 MHz FSB.